FIG. 1 shows a typical example of a memory cell incorporated in a memory cell array of a static-type random access memory device. The memory cell is formed by a first series combination of a p-channel MOS type field effect transistor 1 and an n-channel MO type field effect transistor 2 coupled between a source of positive voltage Vdd and the ground, a second series combination of a p-channel MOS type field effect transistor 3 and an n-channel MOS type field effect transistor 4 coupled in parallel to the first series combination between the source of positive voltage Vdd and the ground, and two switching transistors 5 and 6 each formed by, for example, an n-channel MOS type field effect transistor. The first and second series combinations serve as two complementary MOS (metal-oxide-semiconductor) field effect transistors. First and second memory nodes 7 and 8 are provided between the p-channel MOS type field effect transistor 1 and the n-channel MOS type field effect transistor 2 and between the p-channel MOS type field effect transistor 3 and the n-channel MOS type field effect transistor 4, respectively. The first memory node 7 is coupled to gate electrodes of the p-channel MOS type field effect transistor 3 and the n-channel MOS type field effect transistor 4, and, on the other hand, the second memory node 8 is coupled to gate electrodes of the p-channel MOS type field effect transistor 1 and the n-channel MOS type field effect transistor 2. Between the first and second memory nodes 7 and 8 and a bit line pair consisting of two bit lines 9 and 10 are provided the switching transistors 5 and 6 which has respective gate electrodes commonly coupled to a word line 11. The memory cell thus arranged is capable of preserving a data bit of logic "0" level or logic "1" level depending upon complementary voltage levels on the bit line pair. Namely, when an address specified by an address signal is assigned to the memory cell, the word line 11 goes up to a positive high voltage level, then the switching transistors 5 and 6 turn on to provide conduction paths between the bit line pair and the first and second memory nodes 7 and 8. The complementary voltage levels propagate the conduction paths and reach the memory nodes 7 and 8. The complementary voltage levels at the memory nodes 7 and 8 allow or do not allow the respective complementary MOS field effect transistors to shift to the opposite states, respectively, thereby preserving a new data bit represented by the complementary voltage levels.
As described above, the memory cell is implemented by the complementary MOS field effect transistors, and the structure of a typical complementary MOS field effect transistor is illustrated in FIG. 2 of the drawings. In FIG. 2, an n-type deep well 21 is formed in a p-type semiconductor substrate 22, and a p-channel MOS-type field effect transistor 23 and an n-channel MOS-type field effect transistor 24 are provided in the n-type well 21 and the p-type semiconductor substrate 22, respectively. Namely, the n-type well 21 is doped with p-type impurity atoms to form source/drain regions 25 and 26, and an oxide film 27 and a gate electrode 28 are stacked in succession on a channel region between the source/drain regions 25 and 26, thereby forming the p-channel MOS type field effect transistor 23. On the other hand, the p-type semiconductor substrate 22 is doped with n-type impurity atoms to form source/drain regions 29 and 30, and a oxide film 31 and a gate electrode 32 are stacked on a channel region between the source/drain regions 29 and 30 in a similar manner to the p-channel MOS type field effect transistor 23. The complementary MOS type field effect transistor thus arranged have the p-channel MOS type field effect transistor 23 and the n-channel MOS type field effect transistor 24 on the same semiconductor substrate 22 in close relationship to each other. Then, a wide isolating region 33 is needed along the boundary between the n-type deep well 21 and the p-type semiconductor substrate 22. The wide isolating region 33 consumes a real estate of the semiconductor substrate 22, so that a problem is encountered in that the memory cell array is hardly increased in memory cell density.
A lot of solutions have been proposed to overcome the problem encountered in the prior-art memory cell illustrated in FIG. 2. One of the solutions is disclosed in "A NEW FULL CMOS SRAM CELL STRUCTURE " in International Electron Device Meeting, 1984, pages 67 to 70. The memory cell structure described in the above paper is illustrated in FIG. 3 and fabricated on an n-type semiconductor substrate 36. The n-type semiconductor substrate 36 is doped with p-type impurity atoms to form a p-type well 37, and the p-type well 37 in turn is doped with n-type impurity atoms for formation of source/drain regions 38 and 39. Over that area between the source/drain regions 38 and 39 is stacked an oxide film 40 and a gate electrode 41 which form an n-channel MOS type field effect transistor 42 together with the source/drain regions 38 and 39. The semiconductor substrate 36 has a heavily doped n-type region 43 around the p-type well 37, and the heavily doped n-type region 43 is doped with p-type impurity atoms to form source/drain regions 44 and 45. An oxide film 46 and a gate electrode 47 are formed in succession over a channel region between the source/drain regions 44 and 45, and the source/drain regions 44 and 45, the oxide film 46 and the gate electrode 47 form in combination an n-channel type MOS field effect transistor 48. Thus, the n-channel MOS type field effect transistor 42 is located in adjacent to the p-channel MOS type field effect transistor 48, and, for this reason, a trench-shaped isolating region 49 is formed between the p-type well 37 and the n-type well 43. The trench shaped isolating region 49 occupies a small amount of real estate in comparison with the isolating region 33, so that the static type random access memory device can have the memory cells larger in number than that illustrated in FIG. 2 without reduction in transistor geometry.
However, another problem is encountered in the memory cell structure illustrated in FIG. 3 in that fluctuation in device characteristics tends to take place if the transistor geometry is reduced to increase the number of the memory cells. Namely, when the transistor geometry is reduced, the short channel effect is liable to take place in the component MOS type field effect transistors. As described in connection with FIG. 1, a data bit preserved in the memory cell is represented by the state of the complementary MOS type field effect transistor, i.e., either n-channel or p-channel transistor is turned on. Then, the short channel effect and, the fluctuation of the device characteristics are serious problems to reliability of data bits read out from the static random access memory device.